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holtek 32-bit microcontroller with arm ? cortex?-m3 core ht32f1251/51b/52/53 series datasheet revision: v1.00 date: may 27, 2011
rev. 1.00 2 of 35 may 27, 2011 32-bit arm cortex?-m3 mcu ht32f1251/51b/52/53 table of contents table of contents 1 general description ................................................................................................ 6 2 features ................................................................................................................... 7 core ....................................................................................................................................... 7 on-chip memory .................................................................................................................... 7 flash memory controller ....................................................................................................... 8 reset control unit ................................................................................................................. 8 clock control unit .................................................................................................................. 8 power management ............................................................................................................... 9 analog to digital converter .................................................................................................... 9 analog operational amplifer/comparator ............................................................................. 9 i/o ports ............................................................................................................................... 10 pwm generation and capture timers ................................................................................. 10 watchdog timer ................................................................................................................... 11 real time clock ................................................................................................................... 11 inter-integrated circuit (i 2 c) ................................................................................................. 12 serial peripheral interface (spi) .......................................................................................... 12 universal synchronous asynchronous receiver transmitter (usart) ............................... 13 debug support ..................................................................................................................... 13 package and operation temperature .................................................................................. 13 3 overview ................................................................................................................ 14 device information ............................................................................................................... 14 block diagram ..................................................................................................................... 15 memory map ........................................................................................................................ 16 clock structure .................................................................................................................... 17 pin assignment .................................................................................................................... 18 4 electrical characteristics ..................................................................................... 22 absolute maximum ratings ................................................................................................. 22 dc characteristics ............................................................................................................... 22 on-chip ldo voltage regulator characteristics ................................................................. 22 power consumption ............................................................................................................ 23 reset and supply monitor characteristics ........................................................................... 23 external clock characteristics ............................................................................................. 24 internal clock characteristics .............................................................................................. 25 pll characteristics .............................................................................................................. 26 memory characteristics ....................................................................................................... 26
rev. 1.00 3 of 35 may 27, 2011 32-bit arm cortex?-m3 mcu ht32f1251/51b/52/53 table of contents i/o port characteristics ........................................................................................................ 26 adc characteristics ............................................................................................................ 28 operation amplifer/comparator characteristics ................................................................. 29 gptm characteristics .......................................................................................................... 29 i 2 c characteristics ............................................................................................................... 30 spi characteristics .............................................................................................................. 31 5 package information ............................................................................................ 33 48-pin lqfp (7mmx7mm) outline dimensions ................................................................... 33
rev. 1.00 4 of 35 may 27, 2011 32-bit arm cortex?-m3 mcu ht32f1251/51b/52/53 list of tables list of tables table 1. ht32f125x series features and peripheral list ..................................................................... 14 table 2. ht32f125x pin descriptions ................................................................................................... 20 table 3. absolute maximum ratings ...................................................................................................... 22 table 4. dc operating conditions ......................................................................................................... 22 table 5. ldo characteristics ................................................................................................................. 22 table 6. power consumption characteristics ........................................................................................ 23 table 7. lvd/bod characteristics ......................................................................................................... 23 table 8. high speed external clock (hse) characteristics ................................................................... 24 table 9. low speed external clock (lse) characteristics .................................................................... 24 table 10. high speed internal clock (hsi) characteristics ................................................................... 25 table 11. low speed internal clock (lsi) characteristics ..................................................................... 25 table 12. pll characteristics ................................................................................................................ 26 table 13. flash memory characteristics ................................................................................................ 26 table 14. i/o port characteristics .......................................................................................................... 26 table 15. adc characteristics ............................................................................................................... 28 table 16. opa/cmp characteristics ...................................................................................................... 29 table 17. gptm characteristics ............................................................................................................ 29 table 18. i 2 c characteristics .................................................................................................................. 30 table 19. spi characteristics ................................................................................................................. 31
rev. 1.00 5 of 35 may 27, 2011 32-bit arm cortex?-m3 mcu ht32f1251/51b/52/53 list of figures list of figures figure 1. ht32f125x block diagram ..................................................................................................... 15 figure 2. ht32f125x memory map ........................................................................................................ 16 figure 3. ht32f125x clock structure diagram ...................................................................................... 17 figure 4. ht32f1251b 48lqfp pin assignment ................................................................................... 18 figure 5. ht32f1251/52/53 48lqfp pin assignment ............................................................................ 19 figure 6. i 2 c timing diagram .................................................................................................................. 30 figure 7. spi timing diagram C spi master mode ................................................................................. 31 figure 8. spi timing diagram C spi slave mode and cpha=1 ............................................................. 32
rev. 1.00 6 of 35 may 27, 2011 32-bit arm cortex?-m3 mcu ht32f1251/51b/52/53 general description 1 general description the holtek ht32f125x series of devices are high performance, low power consumption 32-bit microcontrollers based on the arm ? cortex?-m3 processor core. the cortex?-m3 is a next- generation processor core which is tightly coupled with a nested vectored interrupt controller (nvic), systick timer and advanced debug support. the ht32f125x device operates at a frequency of up to 72 mhz with a flash accelerator to obtain maximum effciency. it provides up to 32 kb of embedded flash memory for code/data storage and up to 8 kb of embedded sram memory for system operation and application program usage. a variety of peripherals, such as adc, i 2 c, usart, spi, sw-dp (serial wire debug port), etc., are also implemented in this device series. several power saving modes provide the fexibility for maximum optimisation between wakeup latency and power consumption, an especially important consideration in low power applications. the above features make the ht32f125x device suitable for a wide range of applications, especially in areas such as white goods and application control, power monitor and alarm systems, consumer and handheld equipment, data logging applications and so on.
rev. 1.00 7 of 35 may 27, 2011 32-bit arm cortex?-m3 mcu ht32f1251/51b/52/53 features 2 features core { 32-bit arm ? cortex?-m3 processor core { up to 72 mhz operation frequency { . is/hz (hrstone .) { single-cycle multiplication and hardware division { integrated nested vectored interrupt controller (nvic) { 24-bit systick timer the cortex?-m3 processor is a general-purpose 32-bit processor core especially suitable for products requiring high performance and low power consumption microcontrollers. it offers many new features such as a thumb-2 instruction set, hardware divider, low latency interrupt respond time, atomic bit-banding access and multiple buses for simultaneous accesses. the cortex?-m3 processor is based on the armv7 architecture and supports both thumb and thumb-2 instruction sets. some system peripherals listed below are also provided by cortex?-m3: { internal us atri connected ith icode us, code us, sstem us, riate eripheral us () and deug accesses (aha) { nested vectored interrupt controller (nvic) { lash atch and reakpoint () { data watchpoint and trace (dwt) { instrument trace macrocell (itm) { memory protection unit (mpu) { serial wire jtag debug port (swj-dp) { embedded trace macrocell (etm) { trace port interface unit (tpiu) on-chip memory { to onchip lash memor for instruction/data and option storage { to onchip sa { supports several boot modes the arm ? cortex?-m3 processor is structured in harvard architecture which can use separate evhvwrihwflqvwufwlrqvdqgordgvwruhgdwd7hlqvwufwlrqfrghdqggdwdduherworfdwhglqwh same memory address space but in different address ranges. the maximum address range of the ruwh0lv%vlqfhlwdvdelwevdgguhvvlgwgglwlrqdoodsuhghqhgphpru map is provided by the cortex?-m3 processor to reduce the software complexity of repeated implementation of different device vendors. however, some regions are used by the arm ? cortex?-m3 system peripherals. refer to the arm ? cortex?-m3 technical reference manual for more information. the figure 2. ht32f125x memory map shows the memory map of the +7)vhulhvrighlfhvlqfoglqjrgh650shulshudodqgrwhusuhghqhguhjlrqv
rev. 1.00 8 of 35 may 27, 2011 32-bit arm cortex?-m3 mcu ht32f1251/51b/52/53 features flash memory controller { lash accelerator for maimum effcienc { 32-bit word programming (isp and iap) { flash protection capability to prevent illegal access the flash memory controller, fmc, provides all the necessary functions and pre-fetch buffer for the embedded on-chip flash memory. since the access speed of the flash memory is slower than the cpu, a wide access interface with a pre-fetch buffer is provided for the flash memory in order to reduce the cpu waiting time which will cause cpu instruction execution delays. flash memory rugsurjudpsdjhhudvhiqfwlrqvduhdovrsurlghg reset control unit { supply supervisor: power on reset (por) %urq2whwhfwru%2 programmable low voltage detector (lvd) the reset control unit (rstcu) has three kinds of reset, the power on reset, system reset and 3%qlwuhvhw7hsrhurquhvhwnqrqdvdfroguhvhwuhvhwvwhioovvwhpgulqjsrhus a system reset resets the processor core and peripheral ip components with the exception of the sw-dp controller. the resets can be triggered by an external signal, internal events and the reset generators. clock control unit { external 4 to 16 mhz crystal oscillator { external 32,768 hz crystal oscillator { internal 8mhz rc oscillator trimmed to 1% accuracy at 3.3v operating voltage and 25c operating temperature { internal 32 khz rc oscillator { integrated system clock pll { independent clock gating bits for peripheral clock sources 7horfnrqwuroqlw.8surlghvdudqjhrirvfloodwrudqgforfniqfwlrqv7hvhlqfogh a high speed internal rc oscillator (hsi), a high speed external crystal oscillator (hse), a low speed internal rc oscillator (lsi), a low speed external crystal oscillator (lse), a phase lock loop (pll), a hse clock monitor, clock prescalers, clock multiplexers and clock gating circuitry. 7hforfnvriwh+%3%dqgruwh tm 0duhghulhgiurpwhvvwhpforfn.66 which can come from the hsi, hse or pll. the watchdog timer and real time clock (rtc) use either the lsi or lse as their clock source. the maximum operating frequency of the system core forfn.+%fdqehswr0+ note: e
rev. 1.00 9 of 35 may 27, 2011 32-bit arm cortex?-m3 mcu ht32f1251/51b/52/53 features power management { single 3.3 v power supply: 2.7 v to 3.6 v { integrated 1.8 v ldo regulator for core and peripheral power supply { v % 7 battery power supply for rtc and backup registers { three poer domains ., . and ackup { four power saving modes: sleep, deep-sleep1, deep-sleep2, power-down the power consumption can be regarded as one of the most important issues for many embedded system applications. accordingly the power control unit, pwrcu, in these devices provides many types of power saving modes such as sleep, deep-sleep1, deep-sleep2 and power-down mode. these operating modes reduce the power consumption and allow the application to achieve the best wudghriiehwhhqwhfrqlfwlqjghpdqgvri38rshudwlqjwlphvshhgdqgsrhufrqvpswlrq ( note: battery power supply). analog to digital converter { 12-bit sar adc engine { up to sps conersion rate s at hz, . s at hz { 8 external analog input channels { supply voltage range: 2.7 v ~ 3.6 v { conversion range: v ssa ~ v dda a 12-bit multi-channel adc is integrated in the device. there are a total of 10 multiplexed channels, which include 8 external channels on which the external analog signals can be supplied, and 2 internal channels. if the input voltage is required to remain within a specific threshold window, the analog watchdog function will monitor and detect the signal. an interrupt will then be generated to inform that the input voltage is higher or lower than the set thresholds. there are three conversion modes to convert an analog signal to digital data. the adc can be operated in one shot, continuous and discontinuous conversion modes. analog operational amplifer/comparator { operational amplifers or comparator functions hich are softare confgurale { supply voltage range: 2.7 v ~ 3.6 v 7r2shudwlrqdopsolhuvrpsdudwruv2303duhlpsohphqwhglwlqwhghlfhv7h fdqehfrqjuhghlwhudv2shudwlrqdopsolhuvrudvqdorjrpsdudwruv:hqfrqjuhgdv comparators, they are capable of asserting interrupts to the nvic.
rev. 1.00 10 of 35 may 27, 2011 32-bit arm cortex?-m3 mcu ht32f1251/51b/52/53 features i/o ports { up to 32 gpios { ort a and ort are mapped as eternal interrupts (ti) { almost all i/o pins are tolerant ecept for pins shared ith analog inputs there are up to 32 corresponding registers regardless of the af input or output pins. the external interrupts on the gpio pins of the device have related control and configuration uhjlvwhuvlqwh(whuqdo,qwhuuswrqwuro8qlw(7, pwm generation and capture timers { two 16-bit general-purpose timers (gptm) { up to 4chs pwm compare output or input capture for each gptm { external trigger input 7hhqhudo3usrvh7lphuvnqrqdv370dqg370frqvlvwrirqhelwsgrq frqwhuiruelwdswuhrpsduh5hjlvwhuv5vrqhelwrqwhu5hordg5hjlvwhu55 dqgvhhudofrqwurovwdwvuhjlvwhuv7hfdqehvhgiruddulhwrisusrvhvlqfoglqjjhqhudo time, input signal pulse width measurement or output waveform generation such as single pulse generation or pwm output. the gptm supports an encoder interface using a decoder with two inputs.
rev. 1.00 11 of 35 may 27, 2011 32-bit arm cortex?-m3 mcu ht32f1251/51b/52/53 features watchdog timer { 12-bit down counter with 3-bit prescaler { interrupt or reset event for the system { programmable watchdog timer window function { write protection function the watchdog timer is a hardware timing circuitry that can be used to detect system failures due to software malfunctions. it includes a 12-bit down-counting counter, a prescaler, a wdt counter value register, a wdt delta value register, interrupt related circuits, wdt operation control circuitry and the wdt protection mechanism. the watchdog timer can be operated in an interrupt mode or a reset mode. the watchdog timer will generate an interrupt or a reset when the counter counts down and reaches a zero value. if the software does not reload the counter value before wh:dwfgrj7lphuqghurrffuvdqlqwhuuswruduhvhwlooehjhqhudwhghqwhfrqwhu qghurv,qdgglwlrqdqlqwhuuswruuhvhwlvdovrjhqhudwhgliwhvriwduhuhordgvwhfrqwhu when the counter value is greater than or equal to the wdt delta value. that means the counter pvwehuhordghglwlqdolplwhgwlplqjlqgrvlqjdvshflfphwrg7h:dwfgrj7lphu counter can be stopped while the processor is in the debug mode. the register write protection function can be enabled to prevent it from changing the configuration of the watchdog timer unexpectedly. real time clock { 32-bit up-counter with a programmable prescaler { alarm function { interrupt and wake-up event 7h5hdo7lphorfn57fluflwulqfoghvwh3%lqwhuidfhdelwsfrqwhudfrqwuro register, a prescaler, a compare register and a status register. most of the rtc circuits are located lqwh%dfnsrpdlqhfhswiruwh3%lqwhuidfh7h3%lqwhuidfhlvorfdwhglqwh9 dd18 domain. therefore, it is necessary to be isolated from the iso signal that comes from the power control unit when the v dd18 domain is powered off, i.e., when the device enters the power-down mode. the rtc counter is used as a wakeup timer to generate a system resume from the power- down mode.
rev. 1.00 12 of 35 may 27, 2011 32-bit arm cortex?-m3 mcu ht32f1251/51b/52/53 features inter-integrated circuit (i 2 c) { support both master and slave mode with a frequency of up to 400 khz { provide arbitration function { supports 7-bit and 10-bit addressing mode and general call addressing the i 2 c module is an internal circuit allowing communication with an external i 2 c interface which is an industry standard two line serial interface used for connection to external hardware. these two serial lines are known as a serial data line, sda, and a serial clock line, scl. the i 2 c module provides two data transfer rates: (1) 100 khz in the standard mode or (2) 400 khz in the fast mode. the scl period generation register is used to setup different kinds of duty cycle implementation for the scl pulse. the sda line which is connected to the whole i 2 c bus is a bi-directional data line between the master and slave devices used for the transmission and reception of data. the i 2 c module also has an arbitration detect function to prevent the situation where more than one master attempts to transmit data to the i 2 c bus at the same time. serial peripheral interface (spi) { spi interfaces with a frequency of up to 18 mhz { support both master and slave mode { fifo depth: 8 levels { multi-master and multi-slave operation the serial peripheral interface, spi, provides an spi protocol data transmit and receive function in both master and slave mode. the spi interface uses 4 pins, among which are the serial data input dqgrwswolqhv0,62dqg026,whforfnolqh6.dqgwhvodhvhohfwolqh6(2qh63, ghlfhdfwvdvdpdvwhulffrqwurovwhgdwdrvlqjwh6(dqg6.vljqdovwrlqglfdwhwh start of the data communication and the data sampling rate. to receive a data byte, the streamed gdwdelwvduhodwfhgrqdvshflfforfnhgjhdqgvwruhglqwhgdwduhjlvwhurulqwh5),)2 data transmission is carried in a similar way but with a reverse sequence. the mode fault detection provides a capability for multi-master applications.
rev. 1.00 13 of 35 may 27, 2011 32-bit arm cortex?-m3 mcu ht32f1251/51b/52/53 features universal synchronous asynchronous receiver transmitter (usart) { operating frequency: up to 4.5 mhz { supports both asynchronous and clocked synchronous serial communication modes { irda sir encoder and decoder { rs485 mode with output enable control { full modem function { fifo depth: 16 x 9 bits for both receiver and transmitter the universal synchronous asynchronous receiver transceiver, usart, provides a flexible full duplex data exchange using synchronous or asynchronous transfer. the usart is used to translate data between parallel and serial interfaces, and is also commonly used for rs232 standard frppqlfdwlrq7h8657shulshudoiqfwlrqvssruwvhwshvrilqwhuuswlqfoglqjlqh status interrupt, transmitter fifo empty interrupt, receiver threshold level reaching interrupt, time out interrupt and modem status interrupt. the usart module includes a 16-byte wudqvplwwhu),)27),)2dqgdewhuhfhlhu),)25),)2 software can detect a usart error status by reading the line status register, lsr. the status includes the type and the condition of transfer operations as well as several error conditions uhvowlqjiurp3dulw2huuq)udplqjdqg%uhdnhhqwv 7h8657lqfoghvdsurjudppdeohedgudwhjhqhudwrulflvfdsdeohrigllglqjwh. +%wrsurgfhdforfniruwh8657wudqvplwwhudqguhfhlhu debug support { serial wire debug port - sw-dp { instruction comparators and literal comparators for hardare reakpoint or code / literal patch { 4 comparators for hardware watchpoint { 1-bit asynchronous trace - traceswo package and operation temperature { 48-pin lqfp package { operation temperature range: -40c to +85c
rev. 1.00 14 of 35 may 27, 2011 32-bit arm cortex?-m3 mcu ht32f1251/51b/52/53 overview 3 overview device information most features are common to all devices while the main features distinguishing them are flash memory and sram memory capacities. table 1. ht32f125x series features and peripheral list peripherals HT32F1253 ht32f1252 ht32f1251 ht32f1251b main flash (kb) 31 16 8 8 option bytes flash (kb) 1 1 1 1 sram (kb) 8 4 2 2 timers gptm 2 rtc 1 wdt 1 communication usart 1 spi 1 i 2 c 1 gpio 32 30 exti 16 12-bit adc number of channels 1 8 channels opa/comparator 2 cpu frequency up to 72 mhz operating voltage 2.7 v ~ 3.6 v operating temperature -40 ~ +85 package lqfp48
rev. 1.00 15 of 35 may 27, 2011 32-bit arm cortex?-m3 mcu ht32f1251/51b/52/53 overview block diagram tpiu sw - dp traceswo swdio swclk a p b 1 a p b 0 ahb peripherals flash memory i c o d e d c o d e cortex tm - m 3 processor f max : 72 mhz s y s t e m ahb to apb bridge nvic sram sram controller fmc control registers ckcu / rstcu control registers slave slave slave i n t e r r u p t r e q u e s t 12 -bit sar adc analog opa /cmp powered by v dda vdda vssa cn0 , cp 0 aout 0 cn1 , cp 1 aout 1 usart spi adc opa /cmp gpioa gpiob afio exti i2 c wdt gptm0 gptm1 porb v bak 3 . 3 v lsi 32 khz lse 32, 768 hz breg powered by v bak vldoin vbat v bak pwrsw rtc pwrcu pb [ 15 : 0 ] pa [ 15: 0 ] ur_ tx , ur_ rx ur _ dcd ur_ dsr ur _ dtr ur_ ri ur_ rts / txe ur_ cts / sck spi _ mosi spi _ miso spi _ sck spi _ sel adc _ in 0 . . . adc _ in 7 nrst i 2 c _ sda i 2 c _ scl powered by 3 . 3 v pll f max : 144 mhz por 1 . 8 v rtcout wakeup boot 0 boot 1 flash memory controller c l o ck a n d r e se t co n t r o l xtal 32 kin xtal 32 kout bod lvd xtalin xtalout vldoout vdd 18 hsi 8 mhz hse 4 ~ 16 mhz p o w e r co n t r o l b u s m atrix powered by 1 . 8 v a f a f a f a f af af af a f a f a f a f a f a f af power supply : bus : control signal : alternate function : ldo 1 . 8 v af powered by 1 . 8 v gt 0 _ ch0 gt 0 _ ch3 gt 0 _ eti . . . gt 1 _ ch0 gt 1 _ ch3 gt 1 _ eti . . . master vldoin vssldo note: ht32f1251b does not include the vbat, xtal32kin and xtal32kout pins. figure 1. ht32f125x block diagram
rev. 1.00 16 of 35 may 27, 2011 32-bit arm cortex?-m3 mcu ht32f1251/51b/52/53 overview memory map reserved private peripheral bus reserved apb/ahb bit band alias reserved 0xffff_ffff 0xe010_0000 0xe000_0000 0x4400_0000 0x4200_0000 0x4010_0000 ahb peripherals apb peripherals 0x4008_0000 0x4000_0000 reserved 0x2204_0000 sram bit band alias 0x2200_0000 reserved 0x2000_2000 4 kb on-chip sram 0x2000_1000 2 kb on-chip sram 2 kb on-chip sram 0x2000_0800 0x2000_0000 reserved 0x1ff0_0400 option bytes flash 0x1ff0_0000 reserved 0x1f00_0800 boot loader 0x1f00_0000 reserved 0x0000_7c00 15 kb on-chip flash 8 kb on-chip flash 8 kb on-chip flash 0x0000_0000 code sram peripherals 512 kb 512 kb 32 mb 256 kb 8 kb 4 kb 2 kb 1 kb 2 kb HT32F1253 ht32f1252 ht32f1251(b) 31 kb 16 kb 8 kb ht32f1252 ht32f1251(b) ckcu/rstcu reserved 0x4008_a000 0x4010_0000 0x4008_8000 reserved fmc 0x4008_2000 0x4008_0000 gptm1 reserved 0x4007_0000 0x4006_f000 gptm0 0x4006_e000 reserved 0x4006_b000 rtc/pwrcu 0x4006_a000 reserved 0x4006_9000 wdt 0x4006_8000 reserved 0x4004_9000 i 2 c 0x4004_8000 reserved 0x4002_5000 exti 0x4002_4000 reserved 0x4002_3000 afio 0x4002_2000 reserved 0x4001_c000 gpio b 0x4001_b000 gpio a 0x4001_a000 reserved 0x4001_9000 opa/cmp 0x4001_8000 reserved 0x4001_1000 adc 0x4001_0000 reserved 0x4000_5000 spi 0x4000_4000 reserved 0x4000_1000 usart 0x4000_0000 ahb peripherals apb peripherals 0x0000_2000 0x0000_4000 HT32F1253 notes: 1. for ht32f1251(b), the flash memory space at 0x0000_2000 to 0x0000_7bff and the sram memory space at 0x2000_0800 to 0x2000_1fff are reserved. 2. for ht32f1252, the flash memory space at 0x0000_4000 to 0x0000_7bff and the sram memory space at 0x2000_1000 to 0x2000_1fff are reserved. figure 2. ht32f125x memory map
rev. 1.00 17 of 35 may 27, 2011 32-bit arm cortex?-m3 mcu ht32f1251/51b/52/53 overview clock structure 4-16 mhz hse xtal 8 mhz hsi rc 32 khz lsi rc 32.768 khz lse osc wdtsrc pllsrc ahb prescaler 1,2,4,8 fclk ( free running clock) hclkc ( to cortex-m3) stclk (to systick) adc prescaler 1,2,4,6,8... ck_adc f ck_ahb,max = 72mhz ck_wdt wdten ck_pll/16 ck_hsi/16 ck_hse/16 ck_sys/16 ckout ckoutsrc[2:0] hseen hsien lseen lsien f ck_sys,max = 144mhz ck_lsi ck_lse ck_ahb/16 ck_hsi ck_hse pclk ( to opa, afio gpio port, adc, spi, usart, i2c, gptim, exti, rtc, wdt) 14 pll clock monitor pllen ck_usart ck_lse ck_pll uren cm3en (control by hw) opa0en wdten (apb peripherals clock gating) adcen prescaler 1, 2 f ck_pll,max = 144mhz ck_lsi hclks ( to sram) hclkf ( to flash) cm3en fmcen cm3en sramen 14 1 0 rtcsrc ck_rtc rtcen 1 0 1 0 ck_ahb 000 001 010 011 100 101 110 ck_sys sw[1:0] 0x 11 10 8 legend: hse = high speed external clock hsi = high speed internal clock lse = low speed external clock lsi = low speed internal clock note: 1. control bits lsien & lseen are located at rtc control register (rtccr). 2. ht32f1251b does not include the vbat, xtal32kin and xtal32kout pins. figure 3. ht32f125x clock structure diagram
rev. 1.00 18 of 35 may 27, 2011 32-bit arm cortex?-m3 mcu ht32f1251/51b/52/53 overview pin assignment 48 47 46 45 44 43 42 41 40 39 38 1 2 3 4 5 6 7 8 9 10 11 13 14 15 16 17 18 19 20 21 22 23 35 34 33 32 31 30 29 28 27 26 25 pa0 adc_in0 gt1_eti pa1 adc_in1 - gt0_ch3 pa2 adc_in2 ur_dcd gt0_ch2 pa3 adc_in3 ur_dsr gt0_ch1 pa4 adc_in4 ur_dtr gt0_ch0 pa5 adc_in5 ur_ri spi_mosi pa6 adc_in6 ur_rts /txe spi_miso pa7 adc_in7 ur_cts /sck spi_sck pa8 - ur_rx spi_sel pa9- boot0 - ur_tx - pa10- boot1 - - - - - pb1 xtalout - - pb0 xtalin gt1_ch0 ur_ri spi_mosi pb15 gt1_ch1 ur_dtr spi_miso pb14 gt1_ch2 ur_dsr spi_sck pb13 gt1_ch3 ur_dcd spi_sel pb12 v ss33_2 v dd33_2 gt0_ch0 - pa15 trace swo gt0_ch1 - pa14 swclk gt0_ch2 - pa13 swdio n.c. af0 (default) af1 af2 af3 af1 af2 af3 af0 (default) af1 af2 af3 af0 (default) af1 af2 af3 - v ldoin v ssldo nrst n.c. n.c. n.c. rtcout pb10- wakeup - - - - - - gt0_eti gt0_ch3 pb11 pa11 pa12 ckout i2c_scl i2c_sda v ssa_1 pb7 v dda v ss33_1 v dd33_1 pb6 pb5 pb4 pb3 pb2 v dd18 cn0 cp0 aout0 cn1 cp1 aout1 - - ur_rts /txe ur_cts /sck - - gt0_et1 gt1_eti gt1_ch3 gt1_ch2 gt1_ch1 gt1_ch0 p33 p33 5vt 5vt 5vt 5vt 5vt 33v 33v 5vt 5vt 5vt 5vt p33 p33 5vt 5vt 5vt p18 5vt 5vt 5vt 33v 33v 33v 33v 33v 33v 33v 33v 33v 33v 33v 33v 33v 33v p33 p33 ap ap p18 p33 ap p18 33v 5vt 5vt 3.3 v digital power pad 3.3 v analog power pad 1.8 v power pad 3.3 v i/o pad 5 v tolerance i/o pad high current output 5 v tolerance i/o pad holtek ht32f1251b lqfp48 37 12 24 36 v ssa_2 ap p33 v ss33_3 n.c. af0 (default) v ldoout figure 4. ht32f1251b 48lqfp pin assignment
rev. 1.00 19 of 35 may 27, 2011 32-bit arm cortex?-m3 mcu ht32f1251/51b/52/53 overview 48 47 46 45 44 43 42 41 40 39 38 1 2 3 4 5 6 7 8 9 10 11 13 14 15 16 17 18 19 20 21 22 23 35 34 33 32 31 30 29 28 27 26 25 pa0 adc_in0 gt1_eti pa1 adc_in1 - gt0_ch3 pa2 adc_in2 ur_dcd gt0_ch2 pa3 adc_in3 ur_dsr gt0_ch1 pa4 adc_in4 ur_dtr gt0_ch0 pa5 adc_in5 ur_ri spi_mosi pa6 adc_in6 ur_rts /txe spi_miso pa7 adc_in7 ur_cts /sck spi_sck pa8 - ur_rx spi_sel pa9- boot0 - ur_tx - pa10- boot1 - - - - - pb1 xtalout - - pb0 xtalin gt1_ch0 ur_ri spi_mosi pb15 gt1_ch1 ur_dtr spi_miso pb14 gt1_ch2 ur_dsr spi_sck pb13 gt1_ch3 ur_dcd spi_sel pb12 v ss33_2 v dd33_2 gt0_ch0 - pa15 trace swo gt0_ch1 - pa14 swclk gt0_ch2 - pa13 swdio n.c. af0 (default) af1 af2 af3 af1 af2 af3 af0 (default) af1 af2 af3 af0 (default) af1 af2 af3 - v ldoin v ssldo nrst v bat xtal32k in xtal32k out pb8 pb9 rtcout pb10- wakeup - - - - - - gt0_eti gt0_ch3 pb11 pa11 pa12 ckout i2c_scl i2c_sda - - - - v ssa_1 pb7 v dda v ss33_1 v dd33_1 pb6 pb5 pb4 pb3 pb2 v dd18 cn0 cp0 aout0 cn1 cp1 aout1 - - ur_rts /txe ur_cts /sck - - gt0_et1 gt1_eti gt1_ch3 gt1_ch2 gt1_ch1 gt1_ch0 p33 p33 5vt p33 33v 33v 5vt 5vt 5vt 5vt 33v 33v 5vt 5vt 5vt 5vt p33 p33 5vt 5vt 5vt p18 5vt 5vt 5vt 33v 33v 33v 33v 33v 33v 33v 33v 33v 33v 33v 33v 33v 33v p33 p33 ap ap p18 p33 ap p18 33v 5vt 5vt 3.3 v digital power pad 3.3 v analog power pad 1.8 v power pad 3.3 v i/o pad 5 v tolerance i/o pad high current output 5 v tolerance i/o pad holtek ht32f1251/52/53 lqfp48 37 12 24 36 v ssa_2 ap p33 v ss33_3 n.c. af0 (default) v ldoout figure 5. ht32f1251/52/53 48lqfp pin assignment
rev. 1.00 20 of 35 may 27, 2011 32-bit arm cortex?-m3 mcu ht32f1251/51b/52/53 overview table 2. ht32f125x pin descriptions pin name pins type (note1) io level (note2) description 48 lqfp default function (af0) af1 af2 af3 v ssa_2 1 p ground reference for adc and opa/comparator pa0 2 i/o gpio pa0 adc_in0 gt1_eti gt0_ch3 pa1 3 i/o gpio pa1 adc_in1 gt0_ch2 pa2 4 i/o gpio pa2 adc_in2 ur_dcd gt0_ch1 pa3 5 i/o gpio pa3 adc_in3 ur_dsr gt0_ch0 pa4 6 i/o gpio pa4 adc_in4 ur_dtr spi_mosi pa5 7 i/o gpio pa5 adc_in5 ur_ri spi_miso pa6 8 i/o gpio pa6 adc_in6 ur_rts/txe spi_sck pa7 9 i/o gpio pa7 adc_in7 ur_cts/sck spi_sel pa8 10 i/o 5v-t gpio pa8 ur_rx pa9 11 i/o 5v-t gpio pa9-boot0 ur_tx pa10 12 i/o 5v-t gpio pa10-boot1 v ldoout 13 p ldo 1.8 v output. please put a 10f capacitor to gnd in those pins as close as possible. n.c 14 v ldoin 15 p ldo 3.3 v power source, also connected to the power switch of the backup domain. v ssldo 16 p ldo ground reference nrst 17 i (backup domain) 5v-t external reset pin and external wakeup pin in power-down mode v bat (note3) 18 p vdd 3.3 v for backup domain pb8 (note3) 19 i/o (backup domain) xtal32kin pb8 pb9 (note3) 20 i/o (backup domain) xtal32kout pb9 pb10 21 i/o (backup domain) 5v-t rtcout pb10- wakeup gt0_eti pb11 22 i/o 5v-t gpio pb11 ckout gt0_ch3 pa11 23 i/o 5v-t gpio pa11 i2c_scl pa12 24 i/o 5v-t gpio pa12 i2c_sda pa13 25 i/o 5v-t swdio pa13 gt0_ch2 pa14 26 i/o 5v-t swclk pa14 gt0_ch1 pa15 27 i/o 5v-t traceswo pa15 gt0_ch0 v dd33_2 28 p 3.3 v voltage for digital i/o v ss33_2 29 p ground reference for digital i/o v ss33_3 30 p ground reference for digital core pb12 31 i/o 5v-t gpio pb12 spi_sel ur_dcd gt1_ch3
rev. 1.00 21 of 35 may 27, 2011 32-bit arm cortex?-m3 mcu ht32f1251/51b/52/53 overview pin name pins type (note1) io level (note2) description 48 lqfp default function (af0) af1 af2 af3 pb13 32 i/o 5v-t gpio pb13 spi_sck ur_dsr gt1_ch2 pb14 33 i/o 5v-t gpio pb14 spi_miso ur_dtr gt1_ch1 pb15 34 i/o 5v-t gpio pb15 spi_mosi ur_ri gt1_ch0 pb0 35 i/o xtalin pb0 pb1 36 i/o xtalout pb1 v dd18 37 p 1.8 v voltage for core n.c 38 pb2 39 i/o gpio pb2 cn0 gt1_ch0 pb3 40 i/o gpio pb3 cp0 gt1_ch1 pb4 41 i/o gpio pb4 aout0 ur_rts/txe gt1_ch2 pb5 42 i/o gpio pb5 cn1 gt1_ch3 pb6 43 i/o gpio pb6 cp1 gt1_eti pb7 44 i/o gpio pb7 aout1 ur_cts/sck gt0_eti v dd33_1 45 p 3.3 v voltage for digital i/o v ss33_1 46 p ground reference for digital i/o v dda 47 p 3.3 v analog voltage for adc and opa/comparator v ssa_1 48 p ground reference for adc and opa/comparator notes: 1. i = input, o = output, p = power supply. 2. 5v-t = 5 v tolerant. 3. ht 32f1251b does not include the vbat, xtal32kin and xtal32kout pins. 4. the gpios are in af0 state after vdd18 power on reset (por) except the rtcout pin of backup domain i/o. the rtcout pin is reset by the backup domain power-on-reset (porb) or backup domain software reset (bak_rst bit in bak_cr register). 5. the backup dom ain of i/o pins has driving current capability limitation (< 1ma @ v bat = 3.3 v).
rev. 1.00 22 of 35 may 27, 2011 32-bit arm cortex?-m3 mcu ht32f1251/51b/52/53 electrical characteristics 4 electrical characteristics absolute maximum ratings the following table shows the absolute maximum ratings of the device. these are stress ratings only. stresses beyond absolute maximum ratings may cause permanent damage to the device. note that the device is not guaranteed to operate properly at the maximum ratings. exposure to the absolute maximum rating conditions for extended periods may affect device reliability. table 3. absolute maximum ratings symbol parameter min max unit v dd33 external main supply voltage v ss - 0.3 v ss + 3.6 v v dda external analog supply voltage v ssa - 0.3 v ssa + 3.6 v v bat external battery supply voltage v ss - 0.3 v ss + 3.6 v v in input voltage on 5 v-tolerant i/o v ss - 0.3 v ss + 5.5 v input voltage on other i/o v ss - 0.3 v dd33 + 0.3 v t a operating temperature range -40 +85 c t stg storage temperature range -55 +150 c t j maximum junction temperature 125 c p d total power dissipation 500 mw v esd electrostatic discharge voltage (human body mode) -4000 +4000 v dc characteristics table 4. dc operating conditions ta = 25c, unless otherwise specifed. symbol parameter conditions min typ max unit v dd33 operating voltage of i/o 2.7 3.3 3.6 v v dda analog operating voltage 2.7 3.3 3.6 v v bat operating voltage of battery supply 2.7 3.3 3.6 v v dd18 operating voltage of core power 1.62 1.8 1.98 v on-chip ldo voltage regulator characteristics table 5. ldo characteristics t a = 25c, unless otherwise specifed. symbol parameter conditions min typ max unit v ldoout internal regulator output voltage v ldoin = 3.3 v regulator input 1.71 1.8 1.89 v i dd18 output current v ldoin = 2.4 v regulator input 200 ma c ldo external flter capacitor value for internal core power supply the capacitor value is dependent on the core power current consumption 2.2 10 f
rev. 1.00 23 of 35 may 27, 2011 32-bit arm cortex?-m3 mcu ht32f1251/51b/52/53 electrical characteristics power consumption table 6. power consumption characteristics t a = 25c, unless otherwise specifed. symbol parameter conditions min typ max unit i dd supply current (run mode) v dd33 = v bat = 3.3 v, hse = 8mhz, pll = 144 mhz, f hclk = 72 mhz, f pclk = 72 mhz, all peripherals enabled 47 ma v dd33 = v bat = 3.3 v, hse = 8mhz, pll = 144 mhz, f hclk = 72 mhz, f pclk = 72 mhz, all peripherals disabled 28 ma supply current (sleep mode) v dd = v bat = 3.3 v, hse = 8mhz, pll = 144 mhz, f hclk = 0 mhz, f pclk = 72 mhz, all peripherals enabled 30 ma v dd33 = v bat = 3.3 v, hse = 8mhz, pll = 144 mhz, f hclk = 0 mhz, f pclk = 72 mhz, all peripherals disabled 7 ma supply current (deep-sleep1 mode) v dd33 = v bat = 3.3 v, all clock off (hse/pll/f hclk ), ldo in low power mode , lsi on, rtc on 66 a supply current (deep-sleep2 mode) v dd33 = v bat = 3.3 v, all clock off (hse/pll/f hclk ), ldo off (dmos on) , lsi on, rtc on 11 a supply current (power-down mode) v dd33 = v bat = 3.3 v, ldo off, lse on, lsi off, rtc on 4.2 a v dd33 = v bat = 3.3 v, ldo off, lse on, lsi off, rtc off 4.1 a v dd33 = v bat = 3.3 v, ldo off, lse off, lsi on, rtc on 4.3 a v dd33 = v bat = 3.3 v, ldo off, lse off, lsi on, rtc off 4.2 a i bat battery supply current (power- down mode) v dd33 not present, v bat = 3.3 v, ldo off, lse off, lsi on, rtc on 4 a v dd33 not present, v bat = 3.3 v, ldo off, lse off, lsi on, rtc off 3.9 a notes: 1. hse is the high speed external oscillator while hsi is the 8mhz high speed internal oscillator. 2. lse is the low speed external oscillator while lsi is the 32 khz low speed internal oscillator. 3. rtc means real time clock. 4. co de = while (1) { nop x n } executed in flash (n > 200). reset and supply monitor characteristics table 7. lvd/bod characteristics t a = 25c, unless otherwise specifed. symbol parameter conditions min typ max unit v bod voltage of brown out detector 2.5 v v lvd voltage of low voltage detector lvds (note1) = 00 2.7 v lvds (note1) = 01 2.8 v lvds (note1) = 10 2.9 v lvds (note1) = 11 3.0 v v por voltage of power on reset 1.36 v note: lvds feld is in pwrcu lvdcsr register
rev. 1.00 24 of 35 may 27, 2011 32-bit arm cortex?-m3 mcu ht32f1251/51b/52/53 electrical characteristics external clock characteristics table 8. high speed external clock (hse) characteristics t a = 25c, unless otherwise specifed. symbol parameter conditions min typ max unit f hse high speed external oscillator frequency (hse) v dd33 = 3.3 v 4 16 mhz c hse recommended load capacitance on xtalin and xtalout tbd pf r fhse recommended external feedback resistor between xtalin and xtalout 1.0 m d hse hse oscillator duty cycle 40 60 % i ddhse hse oscillator operating current v dd33 = 3.3 v, t a = 25c 0.96 ma i stbhse hse oscillator standby current v dd33 = 3.3 v, t a = 25c 0.1 a t suhse hse oscillator startup time v dd33 = 3.3 v, t a = 25c 4 ms table 9. low speed external clock (lse) characteristics t a = 25c, unless otherwise specifed. symbol parameter conditions min typ max unit f lse low speed external oscillator frequency (lse) v dd33 = v bat = 3.3 v 32.768 khz c lse recommended load capacitance on xtal32in and xtal32out tbd pf r flse recommended external feedback resistor between xtal32in and xtal32out 10 m d lse lse oscillator duty cycle 40 60 % i ddlse lse oscillator operating current v dd33 = v bat = 3.3 v, lsesm = 0 (normal startup mode) 1.7 a i stblse lse oscillator standby current v dd33 = v bat = 3.3 v, lsesm = 1 (fast startup mode) 3 8 a t sulse lse oscillator startup time v dd33 = v bat = 3.3 v, lsesm = 1 (fast startup mode) 200 ms
rev. 1.00 25 of 35 may 27, 2011 32-bit arm cortex?-m3 mcu ht32f1251/51b/52/53 electrical characteristics internal clock characteristics table 10. high speed internal clock (hsi) characteristics t a = 25c, unless otherwise specifed. symbol parameter conditions min typ max unit f hsi high speed internal oscillator frequency (hsi ) v dd33 = 3.3 v, t a = -40c ~ +85c tbd 8 tbd mhz acc hsi hsi oscillator frequency accuracy factory-trimmed, v dd33 = 3.3 v, t a = 25c -1 +1 % d hsi hsi oscillator duty cycle v dd33 = 3.3 v, f hsi = 8 mhz 35 65 % i ddhsi hsi oscillator operating current v dd33 = 3.3 v, f hsi = 8 mhz 0.92 ma t suhsi hsi oscillator startup time v dd33 = 3.3 v, f hsi = 8 mhz, hsircbl = 0 (hsi ready counter bits length 7 bits ) 17 s note: hsircbl feld is in pwrcu hsircr register table 11. low speed internal clock (lsi) characteristics t a = 25c, unless otherwise specifed. symbol parameter conditions min typ max unit f lsi low speed internal oscillator frequency(lsi) v dd33 = v bat = 3.3 v, t a = -40c ~ +85c 25 32 43 khz i ddlsi lsi oscillator operating current v dd33 = v bat = 3.3 v, t a = 25c 1.0 2 a t sulsi lsi oscillator startup time v dd33 = v bat = 3.3 v, t a = 25c 35 ms
rev. 1.00 26 of 35 may 27, 2011 32-bit arm cortex?-m3 mcu ht32f1251/51b/52/53 electrical characteristics pll characteristics table 12. pll characteristics t a = 25c, unless otherwise specifed. symbol parameter conditions min typ max unit f pllin pll input clock frequency pllv dd18 = 1.8 v 4 16 mhz f pll pll output clock frequency pllv dd18 = 1.8 v 8 144 mhz t lock pll lock time pllv dd18 = 1.8 v tbd ms memory characteristics table 13. flash memory characteristics t a = 25c, unless otherwise specifed. symbol parameter conditions min typ max unit n endu number of guaranteed program /erase cycles before failure. (endurance) v dd18 =1.8 v, t a = -40c ~ +85c 1 kcycles t ret data retention time t a = 25c 100 years t prog word programming time v dd18 = 1.8 v, t a = -40c ~ +85c 40 s t erase page erase time v dd18 = 1.8 v, t a = -40c ~ +85c 20 40 ms t merase mass erase time v dd18 = 1.8 v, t a = -40c ~ +85c 20 40 ms i/o port characteristics table 14. i/o port characteristics t a = 25c, unless otherwise specifed. symbol parameter conditions min typ max unit i il low level input current 3.3 v io v i = 0 v, on-chip pull-up resister disabled. 3 a 5 v-tolerant io 3 a reset pin 3 a i ih high level input current 3.3 v io v i = v dd33, on-chip pull-down resister disabled. 3 a 5 v-tolerant io 3 a reset pin 3 a v il low level input voltage 3.3 v io -0.3 0.8 v 5 v-tolerant io -0.3 0.8 v reset pin -0.3 0.8 v v ih high level input voltage 3.3 v io 2 3.6 v 5 v-tolerant io 2 5.5 v reset pin 2 5.5 v
rev. 1.00 27 of 35 may 27, 2011 32-bit arm cortex?-m3 mcu ht32f1251/51b/52/53 electrical characteristics symbol parameter conditions min typ max unit v hys schmitt trigger input voltage hysteresis 3.3 v io 400 mv 5 v-tolerant io 400 mv reset pin 400 mv i ol low level output current (gpo sink current) 3.3 v 4 ma drive io, v ol = 0.4 v 4 ma 3.3 v 8 ma drive io, v ol = 0.4 v 8 ma 5 v-tolerant 8 ma drive io, v ol =0.4v 8 ma 5 v-tolerant 12 ma drive io, v ol =0.4v 12 ma backup domain io drive @ v bat =3.3v, v ol = 0.4 v, pb8, pb9, pb10. 1 ma i oh high level output current (gpo source current) 3.3v i/o 4 ma drive, v oh =v dd33 -0.4v 4 ma 3.3v i/o 8 ma drive, v oh =v dd33 -0.4v 8 ma 5 v-tolerant i/o 8 ma drive, v oh = v dd33 - 0.4 v 8 ma 5 v-tolerant i/o 12 ma drive, v oh = v dd33 - 0.4 v 12 ma backup domain io drive@v bat =3.3v, v oh = v dd33 - 0.4 v, pb8, pb9, pb10. 1 ma v ol low level output voltage 3.3 v 4 ma drive io, i ol = 4 ma 0.4 v 3.3 v 8 ma drive io, i ol = 8 ma 0.4 v 5 v-tolerant 8 ma drive io, i ol =8ma 0.4 v 5 v-tolerant 12 ma drive io, i ol =12ma 0.4 v v oh high level output voltage 3.3 v 4 ma drive io, i oh = 4 ma v dd33 - 0.4 v v 3.3 v 8 ma drive io, i oh = 8 ma v dd33 - 0.4 v v 5 v-tolerant 8 ma drive io, i oh =8ma v dd33 - 0.4 v v 5 v-tolerant 12 ma drive io, i oh =12ma v dd33 - 0.4 v v r pu internal pull-up resistor 3.3 v i/o 34 74 k 5 v-tolerant i/o 38 89 k r pd internal pull-down resistor 3.3 v i/o 29 86 k 5 v-tolerant i/o 35 107 k
rev. 1.00 28 of 35 may 27, 2011 32-bit arm cortex?-m3 mcu ht32f1251/51b/52/53 electrical characteristics adc characteristics table 15. adc characteristics t a = 25c, unless otherwise specifed. symbol parameter conditions min typ max unit v dda operating voltage 2.7 3.3 3.6 v v adcin a/d converter input voltage range 0 v dda v i adc current consumption v dda = 3.3 v 1 tbd ma i adc_dn power down current consumption v dda = 3.3 v 1 10 ua f adc a/d converter clock 0.7 14 mhz f s sampling rate 0.05 1 mhz f adcconv a/d converter conversion time 14 t adc r i input sampling switch resistance 1 k c i input sampling capacitance no pin/pad capacitance included 5 pf t su startup time 1 us n a/d converter resolution 12 bits inl integral non-linearity error f s = 1 mhz, v dda = 3.3 v - 2 5 lsb dnl differential non-linearity error f s = 1 mhz, v dda = 3.3 v 1 lsb e o offset error 10 lsb e g gain error 10 lsb notes: 1. t adc = 1/f adc . 2. guaranteed by design, not tested in production.
rev. 1.00 29 of 35 may 27, 2011 32-bit arm cortex?-m3 mcu ht32f1251/51b/52/53 electrical characteristics operation amplifer/comparator characteristics table 16. opa/cmp characteristics t a &xqohvvrwkhulvhvshflhg symbol parameter conditions min typ max unit v dda operating voltage 2.7 3.3 3.6 v i opa/cmp typical operating current 230 ua i opa/cmp_dn power down supply current assign registers opaen = 0 and en_opaop = 0 0.1 ua v ios input offset voltage v dda = 3.3 v, anof[5:0] = 100000 -15 15 mv v dda = 3.3 v, after calibration -1 1 mv gv voltage gain 60 100 db u t unit-gain bandwidth 5/ . 1,3 mhz 5/ .&/ s) 1.24 v cm common mode voltage range vdda = 3.3 v v ssa v dda C 0.6 v t rt comparator response time vdda = 3.3 v; input overdrive = 10mv 1 us sr slew rate vdda = 3.3 v; output capacitor load c l =100pf 1.6 v/us note: guaranteed by design, not tested in production. gptm characteristics table 17. gptm characteristics symbol parameter conditions min typ max unit f gptm timer clock source 72 mhz t res timer resolution time 1 1/f gptm f ext external signal frequency on channel 1 ~ 4 1/2 f gptm res timer resolution 16 bits
rev. 1.00 30 of 35 may 27, 2011 32-bit arm cortex?-m3 mcu ht32f1251/51b/52/53 electrical characteristics i 2 c characteristics table 18. i 2 c characteristics symbol parameter conditions min typ max unit f scl scl clock frequency 400 khz t scl(h) scl clock high time 600 ns t scl(l) scl clock low time 1300 ns t fall scl and sda fall time 300 ns t rise scl and sda rise time 300 ns t su(sta) start condition setup time 600 ns t h(sta) start condition hold time 600 ns t su(sda) sda data setup time 100 ns t h(sda) sda data hold time 0 ns t su(sto) stop condition setup time 600 ns t su(sta) t h(sta) t fall t scl(l) t rise t scl(h) t h(sda) t su(sda) t su(sto) scl sda figure 6. i 2 c timing diagram
rev. 1.00 31 of 35 may 27, 2011 32-bit arm cortex?-m3 mcu ht32f1251/51b/52/53 electrical characteristics spi characteristics table 19. spi characteristics symbol parameter conditions min typ max unit f sck sck clock frequency f pclk /4 mhz t sck(h) sck clock high time f pclk /8 ns t sck(l) sck clock low time f pclk /8 ns spi master mode t v(mo) data output valid time 5 ns t h(mo) data output hold time 2 ns t su(mi) data input setup time 5 ns t h(mi) data input hold time 5 ns spi slave mode t su(sel) sel enable setup time 4 t pclk ns t h(sel) sel enable hold time 2 t pclk ns t a(so) data output access time 3 t pclk ns t dis(so) data output disable time 10 ns t v(so) data output valid time 25 ns t h(so) data output hold time 15 ns t su(si) data input setup time 5 ns t h(si) data input hold time 4 ns sck (cpol = 0) sck (cpol = 1) mosi miso mosi miso t sck(h) t sck(l) t sck data valid data valid data valid data valid data valid data valid data valid data valid t v(mo) cpha = 0 cpha = 1 t h(mo) t h(mi) t su(mi) t v(mo) t h(mo) t su(mi) t h(mi) data valid data valid data valid data valid figure 7. spi timing diagram C spi master mode
rev. 1.00 32 of 35 may 27, 2011 32-bit arm cortex?-m3 mcu ht32f1251/51b/52/53 electrical characteristics sck (cpol=0) sck (cpol=1) mosi miso t sck(h) t sck(l) t sck msb/lsb out msb/lsb in t v(so) t h(so) t su(si) t h(si) sel lsb/msb out lsb/msb in t a(so) t su(sel) t dis(so) t h(sel) figure 8. spi timing diagram C spi slave mode and cpha=1
rev. 1.00 33 of 35 may 27, 2011 32-bit arm cortex?-m3 mcu ht32f1251/51b/52/53 package information 5 package information 48-pin lqfp (7mmx7mm) outline dimensions 48-pin lqfp (7mm 7mm) outline dimensions symbol dimensions in inch min. nom. max. a 0.350 0.358 b 0.272 0.280 c 0.350 0.358 d 0.272 0.280 e 0.020 f 0.008 g 0.053 0.057 h 0.063 i 0.004 j 0.018 0.030 k 0.004 0.008 07 symbol dimensions in mm min. nom. max. a 8.90 9.10 b 6.90 7.10 c 8.90 9.10 d 6.90 7.10 e 0.50 f 0.20 g 1.35 1.45 h 1.60 i 0.10 j 0.45 0.75 k 0.10 0.20 07 package information 1 may 12, 2010 symbol dimensions in inch min. nom. max. a 0.350 D 0.358 b 0.272 D 0.280 c 0.350 D 0.358 d 0.272 D 0.280 e D 0.020 D f D 0.008 D g 0.053 D 0.057 h D D 0.063 i D 0.004 j 0.018 D 0.030 k 0.004 D 0.008 0 D 7
rev. 1.00 34 of 35 may 27, 2011 32-bit arm cortex?-m3 mcu ht32f1251/51b/52/53 package information symbol dimensions in mm min. nom. max. a 8.90 D 9.10 b 6.90 D 7.10 c 8.90 D 9.10 d 6.90 D 7.10 e D 0.50 D f D 0.20 D g 1.35 D 1.45 h D D 1.60 i 0.10 j 0.45 D 0.75 k 0.10 D 0.20 0 D 7
rev. 1.00 35 of 35 may 27, 2011 32-bit arm cortex?-m3 mcu ht32f1251/51b/52/53 package information holtek semiconductor inc. (headquarters) no.3, creation rd. ii, science park, hsinchu, taiwan tel: 886-3-563-1999 fax: 886-3-563-1189 http://www.holtek.com.tw holtek semiconductor inc. (taipei sales offce) 4f-2, no. 3-2, yuanqu st., nankang software park, taipei 115, taiwan tel: 886-2-2655-7070 fax: 886-2-2655-7373 fax: 886-2-2655-7383 (international sales hotline) holtek semiconductor inc. (shenzhen sales offce) 5f, unit a, productivity building, no.5 gaoxin m 2nd road, nanshan district, shenzhen, china 518057 tel: 86-755-8616-9908, 86-755-8616-9308 fax: 86-755-8616-9722 holtek semiconductor (usa), inc. (north america sales offce) 46729 fremont blvd., fremont, ca 94538, usa tel: 1-510-252-9880 fax: 1-510-252-9885 http://www.holtek.com copyright ? 2011 by holtek semiconductor inc. the information appearing in this data sheet is believed to be accurate at the time of publication. however, holtek assumes no responsibility arising from the use of the specifications described. the applications mentioned herein are used solely for the purpose of illustration and holtek makes no warranty or uhsuhvhqwdwlrqwkdwvxfkdssolfdwlrqvlooehvxlwdeohlwkrxwixuwkhuprglfdwlrqqruuhfrpphqgvwkhxvh of its products for application that may present a risk to human life due to malfunction or otherwise. holtek's products are not authorized for use as critical components in life support devices or systems. holtek reserves wkhuljkwwrdowhulwvsurgxfwvlwkrxwsulruqrwlfdwlrq)ruwkhprvwxswrgdwhlqirupdwlrqsohdvhylvlwrxu web site at http://www.holtek.com.tw .

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